The phase locked loop is used in order to generate a signal that synchronizes with an input signal. For example, a receiving part of serial data in serial transmission uses the clock and data recovery (CDR) circuit in order to take the received data in a register, and the CDR circuit uses a phase locked loop that has a clock generation circuit having a frequency almost equal to a receiving data rate and being capable of adjusting, its phase by a control signal and a phase comparator for comparing phases of the data and a generated clock and outputting a phase error, and generates a clock synchronizing with the data by controlling the clock generation circuit so that a phase error signal outputted from the phase comparator may be minimized.
Regarding the phase locked loop, US2009/0245449 discloses a technology that, having a frequency synthesizer for multiplying a reference clock inputted from the outside and a phase interpolator for generating a clock that is phase interpolated by the output, generates a synchronizing clock suitable for taking in input serial data by controlling an interpolated value of the phase interpolator according to a phase comparison result between the input serial data and an output clock of the phase interpolator. Moreover, Thomas Toifl et al., “A 72 mW 0.03 mm2 Inductorless 40 Gbps CDR in 65 nm SOI CMOS,” 2007 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS (2007) p. 226 discloses a technology that, having a PLL for generating a clock synchronized in phase with a reference clock inputted from the outside and a voltage controller for controlling a voltage value inputted to the voltage controlled oscillator that constitutes the PLL, generates a synchronizing clock suitable for taking in serial data by controlling a voltage of the voltage controller according to the phase comparison result between the input serial data and the generated clock.